1. Field of the Invention
The present invention generally relates to chip timing adjustment and more particularly to a chip timing adjustment structure which is implemented by programmable delay units and configuration word settings.
2. Description of the Related Art
As the Baud rate increases, the timing performance of fast digital transfer systems becomes more and more critical. This is especially true for multi-channel, fast digital transfer systems because the timing concern in this kind of system is not only for data and clock information, but also for information between channels.
The following factors can cause timing uncertainty. The first factor that can cause timing uncertainty is driver and receiver chip procession variance. The devices used in a fast data transfer system must have a small size to reduce the propagation delay time and the parasitic capacitance. A small portion of geometric variance in a small sized device would cause a relatively big propagation delay time difference.
The second factor that can cause timing uncertainty is noise. A fast driver or receiver requires a wide bandwidth. The wide bandwidth results in more noise and large timing jitter on the transition edges since the noise rms value is proportional to the square root of the bandwidth. In the noisy environment, the clock falling edge or reading edge must be located as close as possible to the middle of a data bit duration in order to obtain a maximum jitters margin.
A third factor that can cause timing uncertainty is the difference of the length of the microstrip lines on a printed circuit board (PCB) between the driver and the receiver. A fast data transfer system must use microstrip lines on the PCB to reduce the attenuation and to reach the impedance matching. However, the signal speed in a microstrip line depends on the dielectric constant of the PCB and is much slower than the speed in vacuum or in air. This causes considerable timing differences for different lengths of microstrip lines in a PCB.
For example, in one structure, a 40 Gb/s data transfer is implemented by 8 channels in parallel, where the Baud rate of each channel is 5 Gb/s and the bit duration of 5 Gb/s is 200 ps. A very popular PCB material, RF4, has the relative dielectric constant of 3.5 to 4.5. Assume that the dielectric constant is between 3.5 and 4.5 (e.g., a middle value of 4). The signal speed in the transmission-line is reversely proportional to the square root of the relative dielectric constant. In such a structure the signal speed in the microstrip line (RF4) is about 67 ps/cm. This means that, if two microstrip lines have more than 1 cm length difference, the propagation delay time difference will be more than 67 ps. Compared with a bit duration time of 200 ps, this 67 ps difference cannot be ignored.
In an actual PCB layout, it is not feasible to keep all microstrip line channel lengths the same length. Therefore, even if the data bit signal and the clock in one channel have proper timing, timing differences would exist among different channels.
According to the problems describe above, even if the chips of a driver or receiver have excellent stand-alone timing performances (and good jitter budgets) when they are mounted on the PCB, serious timing problems could still exist because of driver and receiver chip processing variances, noise, and/or different microstrip line channel lengths. The invention described below overcomes these problems with a novel chip timing adjustment structure which is implemented by programmable delay units and configuration word settings.